1. Field of the Invention
The present invention relates to the use of bumping technology in a stacked die package. More specifically, the present invention employs bumping technology and redistribution technology to minimize a stacked die package height or to provide additional protection for the packaged die.
2. State of the Art
Chip-On-Board technology is used to attach semiconductor dice to a printed circuit board and includes flip chip attachment, wirebonding, and tape automated bonding (xe2x80x9cTABxe2x80x9d). One example of a flip chip is a semiconductor chip that has a pattern or array of electrical terminations or bond pads spaced around an active surface of the flip chip for face-down mounting of the flip chip to a substrate. Generally, such a flip chip has an active surface having one of the following electrical connection patterns: Ball Grid Array (xe2x80x9cBGAxe2x80x9d), wherein an array of minute solder balls is disposed on the surface of a flip chip that attaches to the substrate (xe2x80x9cthe attachment surfacexe2x80x9d); Slightly Larger than Integrated Circuit Carrier (xe2x80x9cSLICCxe2x80x9d), which is similar to a BGA, but has a smaller solder ball pitch and diameter than a BGA; or a Pin Grid Array (xe2x80x9cPGAxe2x80x9d), wherein an array of small pins extends substantially perpendicularly from the attachment surface of a flip chip. The pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto.
With the BGA or SLICC, the arrangement of solder balls or other conductive elements on the flip chip must be a mirror image of the connecting bond pads on the printed circuit board such that precise connection is made. The flip chip is bonded to the printed circuit board by refluxing the solder balls. The solder balls may also be replaced with a conductive polymer. With the PGA, the pin arrangement of the flip chip must be a mirror image of the pin recesses on the printed circuit board. After insertion, the flip chip is generally bonded by soldering the pins into place. An underfill encapsulant is generally disposed between the flip chip and the printed circuit board for environmental protection and to enhance the attachment of the flip chip to the printed circuit board. A variation of the pin-in-recess PGA is a J-lead PGA, wherein the loops of the J""s are soldered to pads on the surface of the circuit board.
Wirebonding and TAB attachment generally begin with attaching a semiconductor chip to the surface of a printed circuit board with an appropriate adhesive, such as an epoxy. In wirebonding, bond wires are attached, one at a time, to each bond pad on the semiconductor chip and extend to a corresponding lead or trace end on the printed circuit board. The bond wires are generally attached through one of three industry-standard wire bonding techniques: ultrasonic bonding, thermocompression bonding and thermosonic bonding. Ultrasonic bonding uses a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld. Thermocompression bonding uses a combination of pressure and elevated temperature to form a weld while thermosonic bonding uses a combination of pressure, elevated temperature, and ultrasonic vibration bursts. With TAB, ends of metal leads carried on an insulating tape, such as a polyimide, are respectively attached to the bond pads on the semiconductor chip and to the lead or trace ends on the printed circuit board. An encapsulant is generally used to cover the bond wires and metal tape leads to prevent contamination.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the semiconductor industry. Greater integrated circuit density is primarily limited by the space available for mounting dice on a substrate such as a printed circuit board. One way to achieve greater integrated circuit density is by attaching two or more semiconductor dice or chips in a single semiconductor assembly. Such devices are generally known as multichip modules (xe2x80x9cMCMxe2x80x9d).
To further increase integrated circuit density, semiconductor dice can be stacked vertically. For example, dice may be stacked vertically on opposite sides of a substrate, or atop each other with intervening insulative layers, prior to encapsulation. U.S. Pat. No. 5,012,323, issued Apr. 30, 1991 to Famworth, teaches combining a pair of dice mounted on opposing sides of a lead frame. An upper, smaller die is back-bonded to the upper surface of the leads of the lead frame via a first adhesively coated, insulated film layer. A lower, larger die is face-bonded to the lower lead frame die-bonding region via a second, adhesively coated, insulative film layer. The wirebonding pads on both the upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum bond wires. The lower die must be slightly larger than the upper die such that the die pads are accessible from above through a bonding window in the lead frame such that gold wire connections can be made to the lead extensions.
U.S. Pat. No. 5,291,061, issued Mar. 1, 1994 to Ball (xe2x80x9cBallxe2x80x9d), teaches a multiple stacked die device containing up to four stacked dice supported on a die-attach paddle of a lead frame, the assembly not exceeding the height of current single die packages, and wherein the bond pads of each die are wirebonded to lead fingers. The low profile of the device is achieved by close-tolerance stacking which is made possible by a low-loop-profile wirebonding operation and thin adhesive layers between the stacked dice. However, Ball requires long bond wires to electrically connect the stacked dice to the lead frame. These long bond wires increase resistance and may result in bond wire sweep during encapsulation.
U.S. Pat. No. 6,222,265 issued Apr. 24, 2001 to Akram et al. teaches a stacked multi-substrate device using flip chips and chip-on-board assembly techniques in which all chips are wire bonded to a substrate. Further, columnar electrical connections attach a base substrate to a stacked substrate.
U.S. Pat. No. 5,952,725 issued Sep. 14, 1999 to Ball teaches a stacked semiconductor device having wafers attached back to back via adhesive. The upper wafer can be attached to a substrate by wire bonding or tape automated bonding. Alternatively, the upper wafer can be attached to a lead frame or substrate, located above the wafer, by flip chip attachment.
Several drawbacks exist with conventional die stacking techniques. As shown in FIG. 1, the top semiconductor die 12 of a semiconductor die stack assembly 10 is typically wire bonded 14 to a substrate 16. With wire bonding, the encapsulant 17 must accommodate the wire loops, increasing the overall package height 18. Further, with wire bonding, a chance of electrical performance problems or shorting exists if the various wires loops come too close to each other. The wire loops can also get swept during packaging, causing further electrical problems. Flip chip attachment overcomes some of these limitations. However, die stacking that relies on flip chip attachment requires the stacked die to be manufactured and vertically aligned to bring complementary circuitry into perpendicular alignment with a lower die.
Similarly, as shown in one configuration of a semiconductor die stack assembly 600 known to the inventor herein (FIG. 6), a top semiconductor die 640 is stacked above a smaller bottom semiconductor die 620 in an active surface 622 of bottom semiconductor die 620 to back side 674 of top semiconductor die 640 arrangement. An optional adhesive layer 626, is shown between bottom semiconductor die 620 and top semiconductor die 640. Peripheral edges 664, 666 of the larger top semiconductor die 640 extend laterally beyond peripheral edges 660, 662 of the bottom semiconductor die 620. Similarly, a stacked board-on-chip assembly 700 is shown in FIG. 7 wherein a top semiconductor die 740 is stacked above a smaller, bottom semiconductor die 720 in a back side 724 of bottom semiconductor die 720 to back side 746 of top semiconductor die 740 arrangement. The peripheral edges 764, 766 of the larger top semiconductor die 740 extend laterally beyond the peripheral edges 760, 762 of the smaller bottom semiconductor die 720. A plurality of external solder balls 772 may be used for electrical connection of the encapsulated stacked board-on-chip assembly 700 to another assembly. FIG. 8 illustrates a configuration of a stacked semiconductor die assembly 800 known to the inventor herein depicting multiple devices on a substrate wherein each device includes two semiconductor dice in a laterally staggered arrangement. The die are stacked such that the active surface 822 of the bottom semiconductor die 820 faces the back side 846 of the top semiconductor die 840. At least one peripheral edge 866, 864 of a top semiconductor die 840 extends laterally beyond a corresponding peripheral edge 862, 860 of a bottom semiconductor die 820. In FIGS. 6, 7 and 8, the top semiconductor dice 640, 740, 840 and the bottom semiconductor dice 620, 720, 820 are electrically connected to a substrate 630, 730, 830 via bond wires 628, 728, 828 that protrude above the uppermost semiconductor dice thereof (or as in FIG. 7, below the lower most semiconductor dice), thus necessitating a higher package height 648, 748, 848.
Therefore, it would be advantageous to develop a stacking technique and assembly for increasing integrated circuit density while either decreasing the overall package height or providing additional protection for the packaged dice without increasing the package height and without the necessity of altering the fabrication of the stacked dice for flip-chip alignment and attachment.
The present invention includes a stacked semiconductor assembly having a minimized package height, while providing protection for intermediate conductive elements that extend between the uppermost semiconductor die thereof and the substrate, and a method of making the same. The assembly includes a first semiconductor die having an active surface and a back side. The active surface includes a plurality of bond pads and a redistribution bond pad circuit thereon. The plurality of bond pads is electrically connected to integrated circuitry of the first semiconductor die, while the redistribution bond pads of the redistribution bond pad circuit are independent and, thus, electrically isolated from the integrated circuitry. Each redistribution bond pad circuit includes a first redistribution bond pad, a second redistribution bond pad positioned adjacent a periphery of the first semiconductor die, and a conductive trace extending between and electrically connecting the first redistribution bond pad and the second redistribution bond pad. The first semiconductor die may be disposed directly on a substrate or a plurality of additional dice may be vertically stacked on the substrate and beneath the first semiconductor die.
A second semiconductor die having an active surface and a back side is disposed above the first semiconductor die such that the active surfaces of both dice are facing one another. The active surface of the second semiconductor die includes a plurality of bond pads thereon. At least one electrical connector extends between at least one bond pad of the plurality of bond pads on the active surface of the second semiconductor die and at least one corresponding first redistribution bond pad of the plurality of redistribution bond pads on the first semiconductor die. The electrical connector also spaces the active surface of the second semiconductor die apart from the active surface of the first semiconductor die a sufficient distance so that bond wires or other discrete conductive elements protruding above the active surface of the first semiconductor die are electrically isolated from the active surface of the second semiconductor die and/or are not collapsed onto one another or bent, kinked or otherwise distorted by the second semiconductor die. Intermediate connective elements electrically connect the second semiconductor die and a substrate by extending from a bond pad on the first semiconductor die to a bond pad on the substrate.
Another embodiment of the invention includes a stacked semiconductor assembly and a method of making the same, wherein the top semiconductor die of the stack has peripheral edges that extend beyond the outer periphery of the immediately underlying semiconductor die. The back side of the lower semiconductor die is secured to a substrate or another semiconductor die or stack of semiconductor dice that are secured to a substrate.
The top semiconductor die is placed above the next lower semiconductor die in an active surface-to-active surface arrangement, with at least a portion of the active surface of the top semiconductor die being exposed beyond the outer periphery of the next lower semiconductor die. At least one electrical connector extends between at least one bond pad on the active surface of the top semiconductor die and at least one bond pad on the substrate to electrically connect the top semiconductor die to the substrate.
Other features and advantages of the present invention will become apparent to those of ordinary skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims.